Paul V. Gratz

PhD Candidate I am a Ph.D. candidate in the Department of Electrical and Computer Engineering at the University of Texas. I am a member of the CART research group, advised by Dr. Stephen W. Keckler. On the TRIPS prototype processor project I designed, implemented and verified the second level memory system, on-chip network and chip-to-chip network. Since the completion of the TRIPS project, my research has focused on load balance and latency reduction in networks-on-chip. I have accepted a position as an assistant professor at Texas A&M starting in Spring 2009.

Research Interests

• On-chip interconnection networks.
• High performance multicore and distributed computer architectures.
• Processor memory systems.

Current Publications

• "Evaluation of the TRIPS Computer System," M. Gebhart, B. A. Maher, K. E. Coons, J. Diamond, P. Gratz, M. Marino, N. Ranganathan, B. Robatmili, A. Smith, J. Burrill, S. W. Keckler, D. Burger, K. S. McKinley. The 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2009 (to appear).
• "Regional Congestion Awareness for Load Balance in Networks-on-Chip," P. Gratz, B. Grot, and S.W. Keckler. The 14th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2008. pdf
• "On-Chip Interconnection Networks of the TRIPS Chip," P. Gratz, C. Kim, K. Sankaralingam, H. Hanson, P. Shivakumar, S.W. Keckler, and D.C. Burger. IEEE Micro, 27(5), pp. 41-50, September/October 2007. pdf
• "TRIPS: A Distributed Explicit Data Graph Execution (EDGE) Microprocessor," M.S. Govindan, K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, P. Gratz, D. Gulati, H. Hanson, C.K. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, S.W. Keckler, and D. Burger, HotChips 19, August 2007.
• "Implementation and Evaluation of a Dynamically Routed Processor Operand Network," P. Gratz, K. Sankaralingam, H. Hanson, P. Shivakumar, R. McDonald, S.W. Keckler, and D.C. Burger. The First IEEE International Symposium on Networks-on-Chips (NOCS), pp 7 - 17, May, 2007. pdf
• "Distributed Microarchitectural Protocols in the TRIPS Prototype Processor," K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M.S. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P.K. Shivakumar, S. W. Keckler, D.C. Burger. The 36th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 480 - 491, December 2006. pdf
• "Implementation and Evaluation of On-Chip Network Architectures," P. Gratz, C. Kim, R. McDonald, S.W. Keckler, and D.C. Burger. 2006 IEEE International Conference on Computer Design (ICCD), pp 477 - 484, October, 2006. pdf
• "Scaling to the End of Silicon with EDGE Architectures," D.C. Burger, S.W. Keckler, K.S. McKinley, et al. IEEE Computer, 37 (7), pp. 44-55, July, 2004.pdf

Contact Information

2706 Salado St. Apt. #201
Austin TX, 78705
http://gratz1.com/pgratz/
email: pgratz AT gratz1 DOT com